Area Efficient 128-point FFT Processor using Mixed Radix 4-2 for OFDM Applications
نویسندگان
چکیده
This paper presents a single-chip 128point FFT processor based on the cached-memory architecture (CMA) with the resource Mixed Radix 4-2 computation element. The 4-2-stage CMA, including a pair of single-port SRAMs, is introduced to increase the execution time of the 2dimensional FFT’s. Using the above techniques, we have designed an FFT processor core which integrates 5,52,000 transistors within an area of 2.8 x 2.8 mm 2 with CMOS 0.35μm triple-layermetal process technology. This processor can execute a 128-point, 36-bit-complex fixed-point data format, 1-dimensonal FFT in 23.2μsec and 2 dimensional FFT in only 23.8 msec at 133 MHz
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